Overview

In this reading we will wrap up our discussion of hardware caches by looking at a few miscellaneous issues, namely how to deal with writes to the cache and the trade-offs involved with various cache design parameters. We’ll also briefly look at the design of a real world cache.

Required Reading

Sections 6.4.5 - 6.4.7 (pp. 630-633) from the course textbook.

Learning Objectives

BASIC Learning Objectives

Each student will be responsible for learning and demonstrating proficiency in the following objectives PRIOR to the class meeting. The reading quiz will test these objectives.

1. Compare and contrast the two major strategies to dealing with write hits.
2. Compare and contrast the two major strategies to dealing with write misses.
3. Explain the role of d-caches, i-caches, and unified caches in modern processors.
4. Describe how cache size, block size, and associativity can impact the hit rate, hit time, and miss penalty.

ADVANCED Learning Objectives

The following objectives should be mastered by each student DURING and FOLLOWING the class session through active work and practice.

1. Describe the trade-off(s) involved with modifying the following cache parameters: cache size, block size, associativity, and write strategy.

Pre-class Exercises

These exercises are geared towards mastering the BASIC learning objectives listed above. You are expected to submit them before class and it is highly recommended that you complete them before attempting the reading quiz.

1. Which of the following write hit policies, write-through or write-back, will be better for the following metrics. For each answer, briefly explain why.

   • Time:
   • Space (i.e. number of bits):

2. What are the main differences between d-caches and i-caches?